#ifndef __D1_REG_CCU_H__
#define __D1_REG_CCU_H__

#define D1_CCU_BASE						(0x02001000ull)
#define CCU_PLL_CPU_CTRL_REG			(0x000ull)
#define CCU_PLL_DDR_CTRL_REG			(0x010ull)
#define CCU_PLL_PERI0_CTRL_REG			(0x020ull)
#define CCU_PLL_PERI1_CTRL_REG			(0x028ull)
#define CCU_PLL_GPU_CTRL_REG			(0x030ull)
#define CCU_PLL_VIDEO0_CTRL_REG			(0x040ull)
#define CCU_PLL_VIDEO1_CTRL_REG			(0x048ull)
#define CCU_PLL_VE_CTRL					(0x058ull)
#define CCU_PLL_DE_CTRL					(0x060ull)
#define CCU_PLL_HSIC_CTRL				(0x070ull)
#define CCU_PLL_AUDIO0_CTRL_REG			(0x078ull)
#define CCU_PLL_AUDIO1_CTRL_REG			(0x080ull)
#define CCU_PLL_DDR_PAT0_CTRL_REG		(0x110ull)
#define CCU_PLL_DDR_PAT1_CTRL_REG		(0x114ull)
#define CCU_PLL_PERI0_PAT0_CTRL_REG		(0x120ull)
#define CCU_PLL_PERI0_PAT1_CTRL_REG		(0x124ull)
#define CCU_PLL_PERI1_PAT0_CTRL_REG		(0x128ull)
#define CCU_PLL_PERI1_PAT1_CTRL_REG		(0x12cull)
#define CCU_PLL_GPU_PAT0_CTRL_REG		(0x130ull)
#define CCU_PLL_GPU_PAT1_CTRL_REG		(0x134ull)
#define CCU_PLL_VIDEO0_PAT0_CTRL_REG	(0x140ull)
#define CCU_PLL_VIDEO0_PAT1_CTRL_REG	(0x144ull)
#define CCU_PLL_VIDEO1_PAT0_CTRL_REG	(0x148ull)
#define CCU_PLL_VIDEO1_PAT1_CTRL_REG	(0x14cull)
#define CCU_PLL_VE_PAT0_CTRL_REG		(0x158ull)
#define CCU_PLL_VE_PAT1_CTRL_REG		(0x15cull)
#define CCU_PLL_DE_PAT0_CTRL_REG		(0x160ull)
#define CCU_PLL_DE_PAT1_CTRL_REG		(0x164ull)
#define CCU_PLL_HSIC_PAT0_CTRL_REG		(0x170ull)
#define CCU_PLL_HSIC_PAT1_CTRL_REG		(0x174ull)
#define CCU_PLL_AUDIO0_PAT0_CTRL_REG	(0x178ull)
#define CCU_PLL_AUDIO0_PAT1_CTRL_REG	(0x17cull)
#define CCU_PLL_AUDIO1_PAT0_CTRL_REG	(0x180ull)
#define CCU_PLL_AUDIO1_PAT1_CTRL_REG	(0x184ull)
#define CCU_PLL_CPU_BIAS_REG			(0x300ull)
#define CCU_PLL_DDR_BIAS_REG			(0x310ull)
#define CCU_PLL_PERI0_BIAS_REG			(0x320ull)
#define CCU_PLL_PERI1_BIAS_REG			(0x328ull)
#define CCU_PLL_GPU_BIAS_REG			(0x330ull)
#define CCU_PLL_VIDEO0_BIAS_REG			(0x340ull)
#define CCU_PLL_VIDEO1_BIAS_REG			(0x348ull)
#define CCU_PLL_VE_BIAS_REG				(0x358ull)
#define CCU_PLL_DE_BIAS_REG				(0x360ull)
#define CCU_PLL_HSIC_BIAS_REG			(0x370ull)
#define CCU_PLL_AUDIO0_BIAS_REG			(0x378ull)
#define CCU_PLL_AUDIO1_BIAS_REG			(0x380ull)
#define CCU_PLL_CPU_TUN_REG				(0x400ull)
#define CCU_CPU_AXI_CFG_REG				(0x500ull)
#define CCU_CPU_GATING_REG				(0x504ull)
#define CCU_PSI_CLK_REG					(0x510ull)
#define CCU_AHB3_CLK_REG				(0x51cull)
#define CCU_APB0_CLK_REG				(0x520ull)
#define CCU_APB1_CLK_REG				(0x524ull)
#define CCU_MBUS_CLK_REG				(0x540ull)
#define CCU_DMA_BGR_REG					(0x70cull)
#define CCU_DRAM_CLK_REG				(0x800ull)
#define CCU_MBUS_MAT_CLK_GATING_REG		(0x804ull)
#define CCU_DRAM_BGR_REG				(0x80cull)
#define CCU_RISCV_CLK_REG				(0xd00ull)
#define CCU_RISCV_GATING_REG			(0xd04ull)
#define CCU_RISCV_CFG_BGR_REG			(0xd0cull)

#endif /* __D1_REG_CCU_H__ */
